october 2014 ?2014 fairchild semiconductor corporation FDMD8280 rev.c www.fairchildsemi.com 1 FDMD8280 dual n-channel powertrench ? mosfet FDMD8280 dual n-channe l power trench ? mosfet 80 v, 40 a, 8.2 m features ? max r ds(on) = 8.2 m at v gs = 10 v, i d = 11 a ? max r ds(on) = 11 m at v gs = 8 v, i d = 9.5 a ? ideal for flexible layout in primary side of bridge topology ? termination is lead-free and rohs compliant ? 100% uil tested ? kelvin high side mosfet drive pin-out capability general description this device includes two 80v n-channel mosfets in a dual power (3.3 mm x 5 mm) package. hs source and ls drain internally connected for half/full bridge, low source inductance package, low r ds(on) /qg fom silicon. applications ? synchronous buck : primary switch of half / full bridge converter for telecom ? motor bridge : primary switch of half / full bridge converter for bldc motor ? mv pol : 48v synchronous buck switch power 3.3 x 5 d1 d1 d1 s2 s2 g2 g1 g1r d2/s1 d2/s1 d2/s1 d2/s1 1 2 3 4 5 6 11 12 9 10 8 7 pin 1 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 80 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 40 a drain current -continuous t a = 25 c (note 1a) 11 -pulsed (note 4) 160 e as single pulse avalanche energy (note 3) 150 mj p d power dissipation t c = 25 c 38 w power dissipation t a = 25 c (note 1a) 2.1 power dissipation t a = 25 c (note 1b) 1 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 3.3 c/w r ja thermal resistance, junction to ambient (note 1a) 60 r ja thermal resistance, junction to ambient (note 1b) 130 device marking device package reel size tape width quantity 8280 FDMD8280 power 3.3 x 5 13 ?? 12 mm 3000 units
FDMD8280 dual n-channel powertrench ? mosfet www.fairchildsemi.com 2 ?2014 fairchild semiconductor corporation FDMD8280 rev.c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 80 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 48 mv/c i dss zero gate voltage drain current v ds = 64 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2.03.04.0v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -9 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 11 a 6.6 8.2 m v gs = 8 v, i d = 9.5 a 7.5 11 v gs = 10 v, i d = 11 a, t j = 125 c 10 12.4 g fs forward transconductance v dd = 10 v, i d = 11 a 29 s c iss input capacitance v ds = 40 v, v gs = 0 v f = 1 mhz 2179 3050 pf c oss output capacitance 341 480 pf c rss reverse transfer capacitance 15 25 pf r g gate resistance 0.1 2.7 5.4 t d(on) turn-on delay time v dd = 40 v, i d = 11 a v gs = 10 v, r gen = 6 15 27 ns t r rise time 12 22 ns t d(off) turn-off delay time 26 42 ns t f fall time 8.9 18 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 40 v i d = 11 a 31 44 nc total gate charge v gs = 0 v to 8 v 25 35 nc q gs gate to source charge 9.5 nc q gd gate to drain ?miller? charge 6.6 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 11 a (note 2) 0.8 1.3 v v gs = 0 v, i s = 1.8 a (note 2) 0.7 1.2 t rr reverse recovery time i f = 11 a, di/dt = 100 a/ s 27 43 ns q rr reverse recovery charge 12 22 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. e as of 150 mj is based on starting t j = 25 o c, l = 3 mh, i as = 10 a, v dd = 72 v, v gs = 10 v. 100% tested at l = 0.1 mh, i as = 32 a. 4. pulse id measured at td <= 250 s, refer to fig 11 soa graph for more details. g df ds sf ss a. 60 c/w when mounted on a 1 i n 2 p a d o f 2 o z c o p p e r g df ds sf ss b. 130 c/w when mounted on a minimum pad of 2 oz copper
FDMD8280 dual n-channel powertrench ? mosfet www.fairchildsemi.com 3 ?2014 fairchild semiconductor corporation FDMD8280 rev.c typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 40 80 120 160 v gs = 6 v v gs = 5.5 v v gs = 6.5 v v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0 40 80 120 160 0 1 2 3 4 5 v gs = 6 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6.5 v v gs = 8 v v gs = 5.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage figure 3. -75 -50 -25 0 25 50 75 100 125 150 0.6 0.9 1.2 1.5 1.8 2.1 i d = 11 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) n o r m a l i z e d o n r e s i s t a n c e vs junction temperature figure 4. 45678910 0 10 20 30 40 50 t j = 125 o c i d = 11 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n r e s i s t a n c e v s g a t e t o source voltage figure 5. 24681 0 0 40 80 120 160 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) transfer characteristics figure 6. 0.00.20.40.60.81.01.21.4 0.001 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMD8280 dual n-channel powertrench ? mosfet www.fairchildsemi.com 4 ?2014 fairchild semiconductor corporation FDMD8280 rev.c f i g u r e 7 . g a t e c h a r g e c h a r a c t e r i s t i c s 0 6 12 18 24 30 36 0 2 4 6 8 10 i d = 11 a v dd = 50 v v dd = 40 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30 v f i g u r e 8 . 0.1 1 10 80 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 1 10 100 t j = 125 o c t j = 25 o c t j = 100 o c t av , time in avalanche (ms) i as , avalanche current (a) g a t e l e a k a g e c u r r e n t vs gate to source voltage figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 v gs = 8 v limited by package r t jc = 3.3 o c/w v gs = 10 v i d , drain current (a) o m a x i m u m c o n t i n u o u s d r a i n current vs case temperature figure 11. 0.1 1 10 100 300 0.1 1 10 100 300 curve bent to measured data 10 p s dc 10 ms 1 ms 100 p s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t jc = 3.3 o c/w t c = 25 o c f o r w a r d b i a s s a f e operating area figure 12. 10 -5 10 -4 10 -3 10 -2 10 -1 1 10 100 1000 10000 single pulse r t jc = 3.3 o c/w t c = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
FDMD8280 dual n-channel powertrench ? mosfet www.fairchildsemi.com 5 ?2014 fairchild semiconductor corporation FDMD8280 rev.c figure 13. junction-to-case transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.001 0.01 0.1 1 2 single pulse duty cycle-descending order r(t), normalized effective transient thermal resistance t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: z t jc (t) = r(t) x r t jc r t jc = 3.3 o c/w duty cycle, d = t 1 / t 2 peak t j = p dm x z t jc (t) + t c typical characteristics t j = 25 c unless otherwise noted
FDMD8280 dual n-channel powertrench ? mosfet www.fairchildsemi.com 6 ?2014 fairchild semiconductor corporation FDMD8280 rev.c dimensional outline and pad layout package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild's worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semicond uctor?s online packaging area for th e most recent package drawings: https://www.fairchildsemi.com/eval uate/package-specifications/pack agedetails.html?id=pn_pqde1-x12
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